This invention relates to silicon-on-insulator (SOI) H-transistors for digital technology. More particularly, it relates to a silicon-on-insulator H-transistor layout for gate arrays.
When scaling transistors to smaller geometries, the hot carrier effect becomes a problem. As a result of the electron/hole generation at the drain of an N channel transistor, hole current flows to the substrate contact of the P well. For bulk devices, which do not have a buried oxide layer, the cross-sectional area to the P well contact is large and the resistance is small. On the other hand, thin film SOI devices have a minimal cross-sectional area and a corresponding increase in resistance to the well contact. Further, thin film SOI devices, in which the source and drain junctions terminate on the buried oxide, are such that the only conduction path to the well contact is along the channel, which further reduces the cross-sectional area. Consequently, the same amount of hole current generated in a SOI or silicon on sapphire (SOS) device passes through a much smaller cross-sectional area (when contrasted with a bulk device), which causes a much larger voltage drop in the channel region. This voltage drop lowers the barrier at the source and injects more electrons into the channel region. This increase in current causes a larger amount of hole current to be generated, which results in additional barrier lowering. The cycle continues. The barrier is lowered even more; more electrons are injected into the channel region; more hole current is generated; and the barrier lowers still more. This uncontrolled state, caused by the hot carrier effect, is commonly known as snapback.
When scaling transistors to smaller geometries for mass production, it is also desirable to delay the routing of transistor elements as much as possible, providing maximum flexibility in the assignment of transistors to specific gates. For custom-made orders, it is desirable to produce as much of the order as possible before an order is received, waiting to personalize the transistors until after the request is received. Once the order is received, the specification as to which node of a transistor is to be the drain and which is to be the source can then be made. It is known in the art that gate array architecture provides this flexibility.
One patent which discloses the use of gate arrays is U.S. Pat. No. 4,602,270 to Finegold. Finegold discloses an improved gate array employing long strips of gates instead of current blocks. Isolation of selected adjacent circuits is provided by connecting adjacent transistor gates to opposite power supplies and permanently turning them off.
While Finegold does reveal an improved gate array, this invention also has several drawbacks. One drawback is that the Finegold invention is only useful on bulk devices. It is not compatible, however, with silicon-on-insulator devices which are favored among many persons over bulk devices.
Another drawback of the Finegold invention has been raised by persons in the space community. As previously mentioned, Finegold isolates selected adjacent circuits by connecting adjacent gates to opposite power supplies. The space community has noted that, if a necessary contact is missing, this mistake may not be detectable in the laboratory during routine checking. Unfortunately, it can only be detected after the satellite, or other device, has been launched into space. When orbiting, the satellite is irradiated with cosmic rays and this alters the transistors, causing them to fail. Consequently, because the failed devices are in orbit, they are inaccessible and cannot be repaired.
Accordingly, it is the primary object of the present invention to provide an improved gate array architecture.
It is another object to provide a gate array which can be used with silicon-on-insulator transistors.
It is yet another object to provide a gate array with a plurality of transistors which minimizes the resistive path to substrate node, thus reducing a transistor's tendency to go into an uncontrolled state; therefore, five-volt operation can be more easily obtained.
It is still another object to provide a gate array wherein the personalization of the transistors can be delayed until late in the fabrication process.
It is still a further object to provide a gate array wherein the accuracy of the contacts can be tested in the laboratory.
The above and other objects and advantages of this invention will become more readily apparent when the following description is read in conjunction with the accompanying drawings.